The invention relates to a semiconductor device comprising a semiconductor body having at a surface one or several circuit elements with at least two conductive regions, the surface being coated with an insulating layer on which a conductor track is provided which interconnects the conductive regions through contact windows in the insulating layer and which is recessed into the insulating layer over at least substantially its entire thickness.
The invention also relates to a method of manufacturing a semiconductor device comprising a semiconductor body having at a surface one or several circuit elements with at least two conductive regions, the surface being coated with an insulating layer on which a conductor track is formed which interconnects the conductive regions through contact windows in the insulating layer and which is recessed into the insulating layer over at least substantially its entire thickness. The term "conductive regions" is to be widely interpreted here so as to include: doped semiconductor zones in the semiconductor body, gate electrodes of field effect devices, portions of subjacent wirings, contact surfaces, etc.
It is usual in complicated integrated circuits to use multilayer interconnections with one or several of the lower interconnection layers made of polycrystalline silicon (poly) and/or silicide, and the upper layer or layers made of metal, such as Al. It is usual thereby to connect poly tracks (or silicide tracks) and monocrystalline zones in the body to the first metal layer by means of metal plugs. These mostly contain W, or TiW and W. The first metal layer is also connected to the second metal layer by means of plug connections.
A semiconductor device and a method of the kind described in the opening paragraph are described in the publication "Reverse Pillar and Maskless Contact - Two novel recessed metal schemes and their comparisons to conventional VLSI metallization schemes" by J. L. Yeh et al. in IEEE Proc. VLSI MIC, pp. 95-100, Santa Clara 1988. In this known method, a mask which is the inverted image of the interconnection pattern in the insulating layer is used for etching a pattern corresponding to the interconnection pattern over part of the thickness of the insulating layer. The contact windows are then formed by means of an additional photoresist mask which covers the insulating layer with the exception of the contact windows to be formed. Then a metal layer is provided, from which the interconnection pattern is formed by etching back. The interconnection pattern lies recessed in the insulating layer, so that the structure remains planar. In addition, no plugs are required for the connections between the interconnection pattern and semiconductor zones or poly tracks.